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x t janua r y 1 9 99 intel and p en t i u m are r e g i s tere d tra d e m arks of intel corp o ra t i on . i 2 c i s a l i cen s e d t r ade m ar k o f phil i p s e l ect r o n i cs , n.v. a m er i can m i crosys t e m s, inc. reserves t h e r i gh t to ch a nge t h e det a il s p ec if i c a- t i on s as m ay be req u i re d to p e r m i t i m prove m ents i n the de s i g n o f i ts p roduct s . 1.13.99 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 1.0 features generates up t o e ig h te e n l o w-s k ew, n o n-i n ver t i n g cloc k s f r o m one clock input su p ports up to f our sd r am d i mms uses eit h er i 2 c ? -bus or smbus serial in t er f ac e with rea d and w rite capa b ili t y f or in d ivi d u a l clock outp u t control outpu t en a ble p in t r istates a ll clock outputs t o f acili- tate board testing clock outputs s k ew- m atched t o less th a n 2 50ps less than 5ns p r op a ga t ion d e l a y output i m pedance: 17 w a t 0 . 5v dd seria l in t er f ace i/o m eet i 2 c speci f ications; a l l ot h er i/o are l v tt l/lvcmos-co m pati b le five di ff ererent p in c o n f igura t i o ns availa b l e : fs6050 : 1 8 cl o c k ou t pu t s i n a 4 8-pi n ssop fs6051 : 1 0 cl o ck ou t pu t s i n a 2 8-pi n soic, ssop fs6053 : 1 3 cl o c k ou t pu t s i n a 2 8-pi n soic fs6054 : 1 4 cl o c k ou t pu t s i n a 2 8-pi n soic fs6057 : 1 7 cl o c k ou t pu t s i n a 3 2-pi n soic figure 1: block diagram (fs6050) s e r i a l int e r f a ce s dr a m_( 0 :1) s c l sda c l k _ in oe fs6050 s dr a m_( 2 :3) s dr a m_( 4 :5) s dr a m_( 6 :7) s dr a m_( 8 :9) sdr a m_ ( 1 0 : 1 1) sdr a m_ ( 1 2 : 1 3) sdr a m_ ( 1 4 : 1 5) sdr a m _ 16 vss _ i 2 c v d d _ i 2 c vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd sdr a m _ 17 vss vdd 18 2.0 description t h e fs60 5 0 f a m il y of cmos c lock f anout bu f f er ics are desi g ned f or h igh-s p eed m otherb o ard a p p lica t i o ns, such as int e l p en t ium ? ii pc 1 00-bas e d s y ste m s wit h 1 0 0 mhz sd r am. up t o eight e e n bu f f ered, non-i n verting c lock outputs are f anned-o u t f r o m on e clock inpu t . i n dividu a l cloc k s are s k ew m atched t o less t h an 2 5 0 ps a t 1 0 0 m h z . m u l t i p le p o wer a n d grou n d su p plies re d uce t h e e ff ects of supply noise on d e vice per f or m ance. under i 2 c-bus cont r ol , i n dividu a l clock outputs m a y b e turned on or o f f . an active - l o w ou t pu t en a ble is a v a ila b le to f orce all the clock outputs t o a tristate l e v e l f or s y stem testi n g. figure 2: pi n configuration (fs6050) 1 48 2 3 4 5 6 7 8 47 46 45 44 43 42 41 ( r es er v ed) ( r es er v ed) vd d s dra m_ 0 s dra m_ 1 vss vd d s dra m_ 2 vs s sd r a m _14 sd r a m _15 ( r es er v e d) vd d ( r es er v e d) 9 10 11 12 13 14 15 16 s dra m_ 3 vss cl k _ i n vd d s dra m_ 4 s dra m_ 5 vss vd d 17 18 19 20 21 22 23 s dra m_ 6 s dra m_ 7 vss vd d s dra m_ 1 6 vss v dd_ i 2 c 40 39 38 37 36 35 34 33 sd r a m _10 sd r a m _11 vd d oe sd r a m _13 sd r a m _12 vs s vd d 32 31 30 29 28 27 26 vs s_i 2 c vs s sd r a m _17 vd d sd r a m _ 9 sd r a m _ 8 vs s 24 sd a 25 sc l vd d vs s fs6050 48-pin ss o p figure 3: pi n configuration (fs6051) 1 2 3 4 5 6 7 8 vd d sd r a m _ 0 sd r a m _ 1 vss vd d sd r a m _ 2 vs s s dra m _ 1 4 s dra m _ 1 5 vd d 9 10 11 12 13 14 15 16 sd r a m _ 3 vss cl k _ i n vd d 17 18 19 20 21 22 23 s dra m_ 1 6 vss v dd_ i 2 c vd d oe s dra m _ 1 3 s dra m _ 1 2 vs s vd d 28 27 26 v ss_i 2 c vs s s dra m _ 1 7 24 sd a 25 sc l fs6051 28-pin soi c , ss o p additional pin configurations are noted on page 3
x t january 1999 1.13.99 2 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 table 1: pin descriptions key: ai = analog input; ao = analog output; di = digital input; di u = input with internal pull-up; di d = input with internal pull-down; dio = digital input/output; di-3 = three-level digital input, do = digital output; p = power/ground; # = active low pin pin (fs6050) pin (fs6051) pin (fs6053) pin (fs6054) pin (fs6057) type name description 11 9 9 9 9 di clk_in clock input for sdram clock outputs 25 15 15 15 17 di u scl serial clock input 24 14 14 14 16 di u o sda serial data input/output 4 2 2 2 2 do sdram_0 5 3 3 3 3 do sdram_1 8 6 6 6 6 do sdram_2 9 7 7 7 7 do sdram_3 13 - - - 10 do sdram_4 14 - - - 11 do sdram_5 17 - 10 10 12 do sdram_6 18 - 11 11 13 do sdram_7 sdram clock outputs (byte 0) 31 - 18 18 20 do sdram_8 32 - 19 19 21 do sdram_9 35 - - - 22 do sdram_10 36 - - - 23 do sdram_11 40 22 22 22 26 do sdram_12 41 23 23 23 27 do sdram_13 44 26 26 26 30 do sdram_14 45 27 27 27 31 do sdram_15 sdram clock outputs (byte 1) 21 11 12 12 14 do sdram_16 28 18 - 17 - do sdram_17 sdram feedback clock outputs (byte 2) 38 20 - 20 - di u oe output enable tristates all clock outputs when low 3, 7, 12, 16, 20, 29, 33, 37, 42, 46 1, 5, 10, 19, 24, 28 1, 5, 20, 24, 28 1, 5, 24, 28 1, 5, 24, 28, 32 pvdd 3.3v 5% power supply for sdram clock buffers 23 13 13 13 15 p vdd_i 2 c 3.3v 5% power supply for serial communications 6, 10, 15, 19, 22, 27, 30, 34, 39, 43 4, 8, 12, 17, 21, 25 4, 8, 17, 21, 25 4, 8, 21, 25 4, 8, 19, 25, 29 p vss ground for sdram clock buffers 26 16 16 16 18 p vss_i 2 c ground for serial communications 1, 2, 47, 48 - - - - - (reserved) reserved 3.0 programming information table 2: clock enable configuration control inputs clock outputs (mhz) oe sdram_0:3 sdram_4:7 sdram_8:11 sdram_12:15 sdram_16:17 0 tristate tristate tristate tristate tristate 1 clk_in clk_in clk_in clk_in clk_in
x t january 1999 1.13.99 3 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 3.1 power-up initialization all outputs are enabled and active upon power-up, and all output control register bits are initialized to one. the outputs must be configured at power-up and are not expected to be configured during normal operation. inac- tive outputs are held low and are disabled from switching. 3.1.1 unused outputs outputs that are not used in versions of this device with a reduced pinout are still operational internally. to reduce power dissipation and crosstalk effects from the unloaded outputs, it is recommended that these outputs be shut off via the control registers. 3.2 register programming a logic-one written to a valid bit location turns on the as- signed output clock. likewise, a logic-zero written to a valid bit location turns off the assigned output clock. any unused or reserved register bits should be cleared to zero. serial bits are written to this device in the order shown in table 3. table 3: register summary serial bit data byte clock output 0 (msb) sdram_7 1 sdram_6 2 sdram_5 3 sdram_4 4 sdram_3 5 sdram_2 6 byte 0 sdram control register 0 sdram_1 7 (lsb) sdram_0 8 (msb) sdram_15 9 sdram_14 10 sdram_13 11 sdram_12 12 sdram_11 13 sdram_10 14 byte 1 sdram control register 1 sdram_9 15 (lsb) sdram_8 16 (msb) sdram_17 17 sdram_16 18 reserved 19 reserved 20 reserved 21 reserved 22 byte 2 sdram control register 2 reserved 23 (lsb) reserved figure 4: pin configuration (fs6053) figure 5: pin configuration (fs6054) figure 6: pin configuration (fs6057) 1 2 3 4 5 6 7 8 vdd sdram_0 sdram_1 vss vdd sdram_2 vss sdram_14 sdram_15 vdd 9 10 11 12 13 14 15 16 sdram_3 vss clk_in sdram_6 17 18 19 20 21 22 23 sdram_7 sdram_16 vdd_i 2 c sdram_9 vdd sdram_13 sdram_12 vss vdd 28 27 26 vss_i 2 c vss sdram_8 24 sda 25 scl fs6053 28-pin soic 1 2 3 4 5 6 7 8 vdd sdram_0 sdram_1 vss vdd sdram_2 vss sdram_14 sdram_15 vdd 9 10 11 12 13 14 15 16 sdram_3 vss clk_in sdram_6 17 18 19 20 21 22 23 sdram_7 sdram_16 vdd_i 2 c sdram_9 oe sdram_13 sdram_12 vss vdd 28 27 26 vss_i 2 c sdram_17 sdram_8 24 sda 25 scl fs6054 28-pin soic 1 2 3 4 5 6 7 8 vdd sdram_0 sdram_1 vss vdd sdram_2 vss sdram_14 sdram_15 vdd 9 10 11 12 13 14 31 30 sdram_3 vss clk_in sdram_4 17 18 19 20 21 22 23 sdram_5 sdram_6 vdd_i 2 c vdd sdram_13 sdram_12 vss vdd 28 27 26 vss_i 2 c vss sdram_8 24 sda 25 scl fs6057 15 29 16 32 sdram_7 sdram_16 sdram_9 sdram_10 sdram_11 32-pin soic
x t january 1999 1.13.99 4 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 table 4: byte 0 - sdram control register 0 register bit clock output description output pin (fs6050) output pin (fs6051) output pin (fs6053) output pin (fs6054) output pin (fs6057) 7 sdram_7 on (1) / off (0) pin 18 - pin 11 pin 11 pin 13 6 sdram_6 on (1) / off (0) pin 17 - pin 10 pin 10 pin 12 5 sdram_5 on (1) / off (0) pin 14 - - - pin 11 4 sdram_4 on (1) / off (0) pin 13 - - - pin 10 3 sdram_3 on (1) / off (0) pin 9 pin 7 pin 7 pin 7 pin 7 2 sdram_2 on (1) / off (0) pin 8 pin 6 pin 6 pin 6 pin 6 1 sdram_1 on (1) / off (0) pin 5 pin 3 pin 3 pin 3 pin 3 0 sdram_0 on (1) / off (0) pin 4 pin 2 pin 2 pin 2 pin 2 table 5: byte 1 - sdram control register 1 register bit clock output description output pin (fs6050) output pin (fs6051) output pin (fs6053) output pin (fs6054) output pin (fs6057) 15 sdram_15 on (1) / off (0) pin 45 pin 27 pin 27 pin 27 pin 31 14 sdram_14 on (1) / off (0) pin 44 pin 26 pin 26 pin 26 pin 30 13 sdram_13 on (1) / off (0) pin 41 pin 23 pin 23 pin 23 pin 27 12 sdram_12 on (1) / off (0) pin 40 pin 22 pin 22 pin 22 pin 26 11 sdram_11 on (1) / off (0) pin 36 - - - pin 23 10 sdram_10 on (1) / off (0) pin 35 - - - pin 22 9 sdram_9 on (1) / off (0) pin 32 - pin 19 pin 19 pin 21 8 sdram_8 on (1) / off (0) pin 31 - pin 18 pin 18 pin 20 table 6: byte 2 - sdram control register 2 register bit clock output description output pin (fs6050) output pin (fs6051) output pin (fs6053) output pin (fs6054) output pin (fs6057) 23 sdram_17 on (1) / off (0) pin 28 pin 18 - pin 17 - 22 sdram_16 on (1) / off (0) pin 21 pin 11 pin 12 pin 12 pin 14 21 reserved (set to 0) - - - - - 20 reserved (set to 0) - - - - - 19 reserved (set to 0) - - - - - 18 reserved (set to 0) - - - - - 17 reserved (set to 0) - - - - - 16 reserved (set to 0) - - - - -
x t january 1999 1.13.99 5 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 4.0 dual serial interface control this integrated circuit is a read/write slave device that supports both the inter ic bus (i 2 c-bus) and the system management bus (smbus) two-wire serial interface pro- tocols. the unique device address that is written to the device determines whether the part expects to receive smbus commands or i 2 c commands. since smbus is derived from the i 2 c-bus, the protocol for both bus types is very similar. in general, the bus has to be controlled by a master de- vice that generates the serial clock scl, controls bus access, and generates the start and stop conditions while the device works as a slave. both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. a device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver. bus logic levels and timing parameters noted herein fol- low i 2 c-bus convention. logic levels are based on a per- centage of vdd. a logic-one corresponds to a nominal voltage of vdd, while a logic-zero corresponds to ground (vss). 4.1 bus conditions data transfer on the bus can only be initiated when the bus is not busy. during the data transfer, the data line (sda) must remain stable whenever the clock line (scl) is high. changes in the data line when the clock line is high is interpreted by the device as a start or stop condition. both i 2 c-bus and smbus protocols define the following conditions on the bus. refer to figure 13: bus timing data for more information. 4.1.1 not busy both the data (sda) and clock (scl) lines remain high to indicate the bus is not busy. 4.1.2 start data transfer a high to low transition of the sda line while the scl in- put is high indicates a start condition. all commands to the device must be preceded by a start condition. 4.1.3 stop data transfer a low to high transition of the sda line while scl is held high indicates a stop condition. all commands to the device must be followed by a stop condition. 4.1.4 data valid the state of the sda line represents valid data if the sda line is stable for the duration of the high period of the scl line after a start condition occurs. the data on the sda line must be changed only during the low period of the scl signal. there is one clock pulse per data bit. each data transfer is initiated by a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is determined by the master device, and can continue indefinitely. however, data that is overwritten to the de- vice after the data registers are filled will overflow from the last register into the first register, then the second, and so on, in a first-in, first-overwritten fashion. 4.1.5 acknowledge when addressed, the receiving device is required to gen- erate an acknowledge after each byte is received. the master device must generate an extra clock pulse to co- incide with the acknowledge bit. the acknowledging de- vice must pull the sda line low during the high period of the master acknowledge clock pulse. setup and hold times must be taken into account. the master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been read (clocked) out of the slave. in this case, the slave must leave the sda line high to allow the master to generate a stop condition. 4.2 bus operation and commands all programmable registers can be accessed via the bi- directional two wire digital interface. the device accepts the random register read/write and the sequential register read/write i 2 c commands. the device also supports the block read/write smbus commands. 4.2.1 i 2 c-bus and smbus device addressing after generating a start condition, the bus master broadcasts a seven-bit device address followed by a r/w bit. note that every device on an i 2 c-bus or smbus must have a unique address to avoid bus conflicts. for an smbus interface, the address of the device is: a6 a5 a4 a3 a2 a1 a0 1101001
x t january 1999 1.13.99 6 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 for an i 2 c-bus interface, the device can support two de- vice addresses to permit multiple devices on one i 2 c-bus. the a2 address bit is ignored and can be set to either a one or a zero. therefore, for an i 2 c-bus interface the device address is: a6 a5 a4 a3 a2 a1 a0 1011x00 4.2.2 i 2 c-bus: random register write procedure random write operations, as shown in figure 7, allow the master to directly write to any register. to initiate a write procedure, the r/w bit that is transmitted after the seven-bit i 2 c device address is a logic-low. this indicates to the ad- dressed slave device that a register address will follow after the slave device acknowledges its device address. the register address is written into the slaves address pointer. following an acknowledge by the slave, the master is allowed to write eight bits of data into the ad- dressed register. a final acknowledge is returned by the device, and the master generates a stop condition. if either a stop or a repeated start condition occurs during a register write, the data that has been trans- ferred is ignored. 4.2.3 i 2 c-bus: random register read procedure random read operations allow the master to directly read from any register. to perform a read procedure, as shown in figure 8, the r/w bit that is transmitted after the seven-bit i 2 c address is a logic-low, as in the register write procedure. this indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. the register address is then written into the slaves address pointer. following an acknowledge by the slave, the master gen- erates a repeated start condition. the repeated start terminates the write procedure, but not until after the slaves address pointer is set. the slave address is then resent, with the r/w bit set this time to a logic-high, indicating to the slave that data will be read. the slave will acknowledge the device address, and then transmits the eight-bit word. the master does not acknowledge the transfer but does generate a stop condition. 4.2.4 i 2 c-bus: sequential register write procedure sequential write operations, as shown in figure 9, allow the master to write to each register in order. the register pointer is automatically incremented after each write. this procedure is more efficient than the random register write if several registers must be written. to initiate a write procedure, the r/w bit that is transmit- ted after the seven-bit i 2 c device address is a logic-low. this indicates to the addressed slave device that a reg- ister address will follow after the slave device acknowl- edges its device address. the register address is written into the slaves address pointer. following an acknowl- edge by the slave, the master is allowed to write data up to the last addressed register before the register address pointer overflows back to the beginning address. an ac- knowledge by the device between each byte of data must occur before the next data byte is sent. registers are updated every time the device sends an acknowledge to the host. the register update does not wait for the stop condition to occur. registers are therefore updated at different times during a sequential register write. 4.2.5 i 2 c-bus: sequential register read procedure sequential read operations allow the master to read from each register in order. the register pointer is automati- cally incremented by one after each read. this proce- dure, as shown in figure 10, is more efficient than the random register read if several registers must be read from. to perform a read procedure, the r/w bit that is trans- mitted after the seven-bit i 2 c address is a logic-low, as in the register write procedure. this indicates to the ad- dressed slave device that a register address will follow after the slave device acknowledges its device address. the register address is then written into the slaves ad- dress pointer. following an acknowledge by the slave, the master gen- erates a repeated start condition. the repeated start terminates the write procedure, but not until after the slaves address pointer is set. the slave address is then resent, with the r/w bit set this time to a logic-high, indicating to the slave that data will be read. the slave will acknowledge the device address, and then transmits all data starting with the initial addressed register. the register address pointer will overflow if the initial register address is larger than zero. after the last byte of data, the master does not acknowledge the transfer but does gen- erate a stop condition.
x t january 1999 1.13.99 7 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 figure 7: random register write procedure (i 2 c-bus) a a data w a from bus host to device s register address p from device to bus host device address register address acknowledge stop condition data acknowledge acknowledge start command write command 7-bit receive device address figure 8: random register read procedure (i 2 c-bus) a r a a a w s register address p s device address start command write command acknowledge register address acknowledge read command acknowledge data no acknowledge stop condition from bus host to device from device to bus host 7-bit receive device address 7-bit receive device address device address data repeat start figure 9: sequential register write procedure (i 2 c-bus) a a a w s p start command write command acknowledge register address acknowledge data data acknowledge data stop command acknowledge acknowledge from bus host to device from device to bus host 7-bit receive device address device address a a register address data data data figure 10: sequential register read procedure (i 2 c-bus) a w s start command write command acknowledge register address acknowledge data acknowledge data stop command acknowledge read command no acknowledge from bus host to device from device to bus host 7-bit receive device address 7-bit receive device address device address a a register address a r a p s device address data data repeat start
x t january 1999 1.13.99 8 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 smbus 4.2.6 smbus: block write the block write command permits the master to write several bytes of data to sequential registers, starting by default at register 0. the block write command, as noted in figure 11, begins with the seven-bit smbus device address followed by a logic- low r/w bit to begin a write command. following an ac- knowledge of the smbus address and r/w bit by the slave device, a command code is written. it is defined that all eight bits of the command code must be zero (0). after the command code of zero and an acknowledge, the host then issues a byte count that describes the number of data bytes to be written. according to smbus convention, the byte count should be a value between 0 and 32; however this slave device ignores the byte count value. following an acknowledge of the byte count, data bytes may be written starting with register 0 and incrementing sequentially. an acknowledge by the device between each byte of data must occur before the next data byte is sent. 4.2.7 smbus: block read the block read command, shown in figure 12, permits the master to read several bytes of data from sequential registers, starting by default at register 0. to perform a block read procedure the r/w bit that is transmitted af- ter the seven-bit smbus address is a logic-low, as in the block write procedure. the write bit resets the register address pointer to zero. following an acknowledge of the smbus address and r/w bit by the slave device, a com- mand code is written. it is defined that all eight bits of the command code must be zero (0). following an acknowledge by the slave, the master gen- erates a repeated start condition. the repeated start terminates the write procedure, but not until after the slaves address pointer is set. the slave smbus ad- dress is then resent, with the r/w bit set this time to a logic-high, indicating to the slave that data will be read. the slave will acknowledge the device address, and then will expect a byte count value (which will be ignored). following the byte count value, the device will take com- mand of the bus and will transmit all the data beginning with register 0. after the last byte of data, the master does not acknowledge the transfer but does generate a stop condition. if the master does not want to receive all the data, the master can not acknowledge the last data byte and then can issue a stop condition of the next clock. figure 11: block write (smbus) a a a data byte 1 write command acknowledge command code acknowledge data acknowledge data stop command data byte n acknowledge byte count acknowledge start command from bus host to device from device to bus host 7-bit receive device address w s device address a a byte count = n p figure 12: block read (smbus) a w a r a a start command write command acknowledge command code acknowledge data acknowledge data stop command acknowledge byte count no acknowledge repeat start read command acknowledge from bus host to device from device to bus host 7-bit receive device address 7-bit receive device address s device address a s device address byte count = n a data byte 1 data byte n p
x t january 1999 1.13.99 9 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 5.0 electrical specifications table 7: absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. exposure to maximum rati ng conditions for extended conditions may affect device performance, functionality, and reliability. parameter symbol min. max. units supply voltage, dc, clock buffers (v ss = ground) v dd v ss -0.5 7 v supply voltage, dc, serial communications v dd_i2c v ss -0.5 7 v input voltage, dc v i v ss -0.5 v dd +0.5 v output voltage, dc v o v ss -0.5 v dd +0.5 v input clamp current, dc (v i < 0 or v i > v dd )i ik -50 50 ma output clamp current, dc (v i < 0 or v i > v dd )i ok -50 50 ma storage temperature range (non-condensing) t s -65 150 c ambient temperature range, under bias t a -55 125 c junction temperature t j 125 c lead temperature (soldering, 10s) 260 c static discharge voltage protection (mil-std 883e, method 3015.7) 2 kv caution: electrostatic sensitive device permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy ele c- trostatic discharge. table 8: operating conditions parameter symbol conditions/description min. typ. max. units supply voltage, clock buffers v dd 3.3v 5% 3.135 3.3 3.465 v supply voltage, serial communications v dd_i2c 3.3v 5% 3.135 3.3 3.465 v ambient operating temperature range t a 070c input frequency f clk 0 133 mhz output load capacitance c l 30 pf serial data transfer rate standard mode 10 100 400 kb/s
x t january 1999 1.13.99 10 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 table 9: dc electrical specifications unless otherwise stated, all power supplies = 3.3v 5%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. negative currents indicate current flows out of the device. parameter symbol conditions/description min. typ. max. units overall (fs6050) supply current, dynamic, with loaded outputs i dd f clk = 100mhz; v dd = 3.47v 180 360 ma supply current, static i ddl outputs low; v dd = 3.47v 0.75 3 ma serial communication inputs/output (sda, scl) high-level input voltage v ih outputs low 2.31 v dd +0.3 v low-level input voltage v il outputs low v ss -0.3 0.9 v hysteresis voltage * v hys outputs low 1.0 v high-level input current i ih -1 1 m a low-level input current (pull-up) i il outputs low; v ih = 0.4v, v dd = 3.47v. note: sda requires an external pull-up to drive the data bus. 51115 m a low-level output sink current (sda) i ol v ol = 0.4v 10 25 ma output enable input (oe) high-level input voltage v ih 2.0 v dd +0.3 v low-level input voltage v il v ss -0.3 0.8 v high-level input current i ih -1 1 m a low-level input current (pull-up) i il v ih = 0.4v; v dd = 3.47v 10 22 30 m a clock input (clk_in) high-level input voltage v ih 2.0 v dd +0.3 v low-level input voltage v il v ss -0.3 0.8 v input leakage current i i -1 1 m a clock outputs (sdram_0:17 3.3v type 4 clock buffer) i oh min v dd = 3.135v, v o = 2.0v -54 -65 high-level output source current i oh max v dd = 3.465v, v o = 3.135v -28 -46 ma i ol min v dd = 3.135v, v o = 1.0v 54 69 low-level output sink current i ol max v dd = 3.465v, v o = 0.4v 33 53 ma z oh v o = 0.5v dd ; output driving high 10 17.9 24 output impedance z ol v o = 0.5v dd ; output driving low 10 16.3 24 w tristate output current i oz -5 5 m a short circuit source current * i osh v o = 0v; shorted for 30s, max. -106 ma short circuit sink current * i osl v o = 3.3v; shorted for 30s, max. 107 ma
x t january 1999 1.13.99 11 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 table 10: ac timing specifications unless otherwise stated, all power supplies = 3.3v 5%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. parameter symbol conditions/description clock (mhz) min. typ. max. units overall 66.67 182 clock skew, maximum; sdram_0 to any sdram pin * t skw measured on the rising edge at 1.5v; c l = 20pf 100 228 ps 66.67 3.7 t plh(min) measured on the rising edge at 1.5v; c l = 20pf 100 3.8 66.67 3.7 t plh(max) measured on the rising edge at 1.5v; c l = 30pf 100 4.0 66.67 3.9 t phl(min) measured on the rising edge at 1.5v; c l = 20pf 100 3.8 66.67 4.2 propagation delay, average; clk_in to any sdram pin * t phl(max) measured on the rising edge at 1.5v; c l = 30pf 100 4.0 ns clock outputs (sdram_0:17 3.3v type 4 clock buffer) 66.67 1.0 t r(min) v o = 0.4v to 2.4v; c l = 20pf 100 0.9 66.67 1.2 rise time * t r(max) v o = 0.4v to 2.4v; c l = 30pf 100 1.0 ns 66.67 1.0 t f(min) v o = 2.4v to 0.4v; c l = 20pf 100 0.7 66.67 1.1 fall time * t f(max) v o = 2.4v to 0.4v; c l = 30pf 100 0.8 ns 66.67 6.5 t kh(min) v o = 2.4v; c l = 20pf 100 3.8 66.67 6.5 clock high time * t kh(max) v o = 2.4v; c l = 30pf 100 3.8 ns 66.67 6.5 t kl(min) v o = 0.4v; c l = 20pf 100 4.6 66.67 6.3 clock low time * t kl(max) v o = 0.4v; c l = 30pf 100 4.5 ns 66.67 49 from rising edge to rising edge at 1.5v; c l = 20pf 100 45 66.67 50 duty cycle * from rising edge to rising edge at 1.5v; c l = 30pf 100 46 % t pzl 4.7 tristate enable delay * t pzh output tristated to output active; c l = 20pf 4.6 ns t plz 6.3 tristate disable delay * t phz output active to output tristated; c l = 20pf 7.9 ns
x t january 1999 1.13.99 12 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 table 11: serial interface timing specifications unless otherwise stated, all power supplies = 3.3v 5%, no load on any output, and ambient temperature range t a = 0c to 70c. parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. min and max characterization data are 3 s from typical. parameter symbol conditions/description min. max. units clock frequency f scl scl 10 400 khz bus free time between stop and start t buf 4.7 m s set up time, start (repeated) t su:sta 4.7 m s hold time, start t hd:sta 4.0 m s set up time, data input t su:dat sda 250 ns hold time, data input t hd:dat sda 300 ns output data valid from clock t aa minimum delay to bridge undefined region of the fall- ing edge of scl to avoid unintended start or stop 3.5 m s rise time, data and clock t r sda, scl 1000 ns fall time, data and clock t f sda, scl 300 ns high time, clock t h scl 4.0 m s low time, clock t l scl 4.7 m s set up time, stop t su:sto 4.0 m s figure 13: bus timing data scl sda ~ ~ ~ ~ ~ ~ stop t su:sto t hd:sta start t su:sta address or data valid data can change figure 14: data transfer sequence scl sda in t hd:dat ~ ~ t hd:sta t su:sta t su:sto t l t h sda out t su:dat ~ ~ ~ ~ t buf t r t f t aa t aa
x t january 1999 1.13.99 13 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 figure 15: sdram_0:17 clock output (3.3v type 4 clock buffer) low drive current (ma) high drive current (ma) voltage (v) min. typ. max. voltage (v) min. typ. max. 0 0 0 0 0 -72 -116 -198 0.4 23 34 53 1 -72 -116 -198 0.65 35 52 83 1.4 -68 -110 -188 0.85 43 65 104 1.5 -67 -107 -184 1 49 74 118 1.65 -64 -103 -177 1.4 61 93 152 1.8 -60 -98 -170 1.5 64 98 159 2 -54 -90 -157 1.65 67 103 168 2.4 -39 -69 -126 1.8 70 108 177 2.6 -30 -56 -107 1.95 72 112 184 3.135 0 -15 -46 3.135 72 112 204 3.3 0 -23 3.6 112 204 3.465 0 -220 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 220 00.511.522.533.54 2xwsxw9rowdjh9 2 x w s x w & x u u h q w p $ min. typ. max. 30 w 50 w 90 w figure 16: dc measurement points v ih 3.3 = 2.0v v il 3.3 = 0.8v v ol 3.3 = 0.4v v oh 3.3 = 2.4v 1.5v 3.3v (device interface) (system interface) figure 17: clock skew measurement point t skw 3.3v 3.3v 1.5v 1.5v figure 18: timing measurement points t kh t r duty cycle t kl t kp 2.4v 1.5v 0.4v t f t plz v ol v oh v ss v dd 10% 90% t phz 50% 50% 50% 50% t pzl t phz
x t january 1999 1.13.99 14 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 6.0 package information table 12: 48-pin ssop (7.5mm/0.300") package dimensions dimensions inches millimeters min. max. min. max. a 0.095 0.110 2.41 2.79 a 1 0.008 0.016 0.203 0.406 a 2 0.088 0.092 2.24 2.34 b 0.008 0.0135 0.203 0.343 c 0.005 0.010 0.127 0.254 d 0.620 0.630 15.75 16.00 e 0.292 0.299 7.42 7.59 e 0.025 bsc 0.64 bsc h 0.400 0.410 10.16 10.41 h 0.010 0.016 0.254 0.410 l 0.024 0.040 0.610 1.02 q 0 8 0 8 be d a 1 seating plane h e 48 1 all radii: 0.005" to 0.01" base plane a 2 x t c l 7 typ. q a table 13: 48-pin ssop (7.5mm/0.300") package characteristics parameter symbol conditions/description typ. units thermal impedance, junction to free-air q ja air flow = 0 m/s 93 c/w lead inductance, self l 11 center lead 3.3 nh lead inductance, mutual l 12 center lead to any adjacent lead 1.6 nh lead capacitance, bulk c 11 center lead to v ss 0.6 pf lead capacitance, mutual c 12 center lead to any adjacent lead 0.2 pf
x t january 1999 1.13.99 15 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 table 14: 28-pin soic (7.5mm/0.300") package dimensions dimensions inches millimeters min. max. min. max. a 0.093 0.104 2.35 2.65 a 1 0.004 0.012 0.10 0.30 a 2 0.08 0.100 2.05 2.55 b 0.013 0.013 0.33 0.51 c 0.009 0.009 0.23 0.32 d 0.697 0.713 17.70 18.10 e 0.291 0.299 7.40 7.60 e 0.05 bsc 1.27 bsc h 0.393 0.419 10.00 10.65 h 0.010 0.030 0.25 0.75 l 0.016 0.05 0.40 1.27 q 0 8 0 8 be d a 1 seating plane h e 28 1 all radii: 0.005" to 0.01" base plane a 2 x t c l 7 typ. q a h x 45 table 15: 28-pin soic (7.5mm/0.300") package characteristics parameter symbol conditions/description typ. units thermal impedance, junction to free-air q ja air flow = 0 m/s 80 c/w lead inductance, self l 11 center lead 2.5 nh lead inductance, mutual l 12 center lead to any adjacent lead 0.85 nh lead capacitance, bulk c 11 center lead to v ss 0.42 pf lead capacitance, mutual c 12 center lead to any adjacent lead 0.08 pf
x t january 1999 1.13.99 16 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 table 16: 28-pin ssop (5.3mm/0.209") package dimensions dimensions inches millimeters min. max. min. max. a 0.068 0.078 1.73 2.00 a 1 0.002 0.008 0.05 0.21 a 2 0.066 0.07 1.68 1.78 b 0.01 0.015 0.25 0.38 c 0.005 0.008 0.13 0.20 d 0.396 0.407 10.07 10.33 e 0.205 0.212 5.20 5.38 e 0.028 bsc 0.65 bsc h 0.301 0.311 7.65 7.90 l 0.022 0.037 0.55 0.95 q 0 8 0 8 h e all radii: 0.005" to 0.01" x t 1 28 be d a 1 seating plane base plane a 2 a c l 7 typ. q table 17: 28-pin ssop (5.3mm/0.209") package characteristics parameter symbol conditions/description typ. units thermal impedance, junction to free-air q ja air flow = 0 m/s 97 c/w lead inductance, self l 11 center lead 2.24 nh lead inductance, mutual l 12 center lead to any adjacent lead 0.95 nh lead capacitance, bulk c 11 center lead to v ss 0.25 pf lead capacitance, mutual c 12 center lead to any adjacent lead 0.07 pf
x t january 1999 1.13.99 17 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 table 18: 32-pin soic (7.5mm/0.300") package dimensions dimensions inches millimeters min. max. min. max. a 0.090 0.100 2.29 2.54 a 1 0.004 0.010 0.10 0.25 a 2 0.086 0.090 2.18 2.29 b 0.014 0.020 0.36 0.51 c 0.006 0.012 0.15 0.32 d 0.810 0.822 20.57 20.88 e 0.292 0.299 7.42 7.60 e 0.05 bsc 1.27 bsc h 0.405 0.419 10.29 10.64 h 0.010 0.030 0.25 0.75 l 0.021 0.041 0.53 1.04 q 0 8 0 8 be d a 1 seating plane h e 32 1 all radii: 0.005" to 0.01" base plane a 2 x t c l 7 typ. q a h x 45 table 19: 32-pin soic (7.5mm/0.300") package characteristics parameter symbol conditions/description typ. units thermal impedance, junction to free-air q ja air flow = 0 m/s 83 c/w lead inductance, self l 11 center lead 2.5 nh lead inductance, mutual l 12 center lead to any adjacent lead 0.85 nh lead capacitance, bulk c 11 center lead to v ss 0.42 pf lead capacitance, mutual c 12 center lead to any adjacent lead 0.08 pf
x t january 1999 1.13.99 18 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 7.0 ordering information ordering code device number font package type operating temperature range shipping configuration 11257-801 fs6050 48-pin (7.5mm/0.300) ssop 0 c to 70 c (commercial) tape and reel 11257-811 fs6050 48-pin (7.5mm/0.300) ssop 0 c to 70 c (commercial) tube 11257-802 fs6051 28-pin (7.5mm/0.300) soic 0 c to 70 c (commercial) tape and reel 11257-812 fs6051 28-pin (7.5mm/0.209) soic 0 c to 70 c (commercial) tube 11257-806 fs6051 28-pin (5.3mm/0.209) ssop 0 c to 70 c (commercial) tape and reel 11257-816 fs6051 28-pin (5.3mm/0.200) ssop 0 c to 70 c (commercial) tube 11257-803 fs6053 28-pin (7.5mm/0.300) soic 0 c to 70 c (commercial) tape and reel 11257-813 fs6053 28-pin (7.5mm/0.300) soic 0 c to 70 c (commercial) tube 11257-804 fs6054 28-pin (7.5mm/0.300) soic 0 c to 70 c (commercial) tape and reel 11257-814 fs6054 28-pin (7.5mm/0.300) soic 0 c to 70 c (commercial) tube 11257-805 fs6057 32-pin (7.5mm/0.300) soic 0 c to 70 c (commercial) tape and reel 11257-815 fs6057 32-pin (7.5mm/0.300) soic 0 c to 70 c (commercial) tube purchase of i 2 c components of american microsystems, inc., or one of its sublicensed associated companies conveys a license under philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. copyright ? 1998 american microsystems, inc. devices sold by ami are covered by the warranty and patent indemnification provisions appearing in its terms of sale only. ami makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the fr eedom of the described devices from patent infringement. ami makes no warranty of merchantability or fitness for any purposes. ami re - serves the right to discontinue production and change specifications and prices at any time and without notice. amis products are intended for use in commercial applications. applications requiring extended temperature range, unusual environmental require- ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom- mended without additional processing by ami for such applications. american microsystems, inc., 2300 buckskin rd., pocatello, id 83201, (208) 233-4690, fax (208) 234-6796, www address: http://www.amis.co m e-mail: t g p@amis.co m
x t january 1999 1.13.99 19 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 8.0 application information 8.1 reduction of emi the primary concern when designing the board layout for this device is the reduction of electromagnetic interfer- ence (emi) generated by the 18 copies of the 100mhz sdram clock. it is assumed the reader is familiar with basic transmission line theory. 8.1.1 layout guidelines to obtain the best performance, noise should be mini- mized on the power and ground supplies to the ic. ob- serve good high-speed board design practices, such as: ? use multi-layer circuit boards with dedicated low im- pedance power and ground planes for the device (denoted as clk vdd and clk gnd in figure 19). the device power and ground planes should be completely isolated from the motherboard power and ground planes by a void in the power planes. ? several low-pass filters using low impedance ferrite ehdgv dw 0+] duh uhfrpphqghg wr ghfr u- ple the device power and ground planes from the motherboard power and ground planes (mb vdd and mb gnd). the beads should span the gap between the power and ground planes. seven beads for power and seven beads for ground are suggested (14 total) so that the clock rise times (1v/ns) can be maintained. ? place 1000pf bypass capacitors as close as possible to the power pins of the ic. use rf-quality low- inductance multi-layer ceramic chip capacitors. six capacitors is optimal, one on each power/ground grouping as shown in figure 19. ? load similar clock outputs equally, and keep output loading as light as possible to help reduce clock skew and power dissipation. ? use equal-length clock traces that are as short as possible. rounded trace corners help reduce reflec- tions and ringing in the clock signal. ? the clock traces must never cross the void area be- tween power/ground planes. each trace must have a complete plane (either vdd or gnd) under the com- plete length of the trace. figure 19: board layout 1 2 4 5 8 9 11 13 14 17 18 21 48 45 41 40 36 28 25 47 mb gnd mb vdd 31 32 44 35 38 24 clk gnd clk vdd void r s 1000pf 1000pf 1000pf 1000pf 1000pf 1000pf clk gnd clk vdd mb gnd mb gnd mb vdd mb vdd signal layer component layer r s r s r s r s r s r s r s r s r s r s r s r s r s r s r s r s r s 8.1.2 output driver termination a signal reflection will occur at any point on a pc-board trace where impedance mismatches exist. reflections cause several undesirable effects in high-speed applica- tions, such as an increase in clock jitter and a rise in electromagnetic emissions from the board. using a prop- erly designed series termination on each high-speed line can alleviate these problems by eliminating signal reflec- tions. figure 20: series termination r s z l z o driver receive line
x t january 1999 1.13.99 20 )6)6)6)6)6 /rz6nhz&orfn)dqrxw%xiihu,&v ,62 series termination adds no dc loading to the driver, and requires less power than other resistive termination methods. further, no extra impedance exists from the signal line to a reference voltage, such as ground. as shown in figure 20 , the sum of the drivers output im- pedance (z o ) and the series termination resistance (r s ) must equal the line impedance (z l ). that is, o l s z z r - = . note that when the source impedance (z o +r s ) is matched to the line impedance, then by voltage division the incident wave amplitude is one-half of the full signal amplitude. 2 ) ( ) ( v z r z r z v v l s o s o i = + + + = the full signal amplitude may take up to twice as long as the propagation delay of the line to develop, reducing noise immunity during the half-amplitude period. note also that the voltage at the receive end must add up to a signal amplitude that meets the receiver switching thresholds. the slew rate of the signal is also reduced due to the additional rc delay of the load capacitance and the line impedance. also note that the output driver impedance will vary slightly with the output logic state (high or low). 8.2 dynamic power dissipation high-speed clock drivers require careful attention to power dissipation. transient power (p t ) consumption can be derived from sw clk load dd t n f c v p = 2 where c load is the load capacitance, v dd is the supply voltage, f clk is the clock frequency, and n sw is the number of switching outputs. the internal heat (junction temperature, t j ) generated by the power dissipation can be calculated from a t ja j t p t + q = where q ja is the package thermal resistance, t a is the ambient temperature, and p t is derived above. 8.3 serial communications connection of devices to a standard-mode implementa- tion of either the i 2 c-bus or the smbus is similar to that shown in figure 21. selection of the pull-up resistors (r p ) and the optional series resistors (r s ) on the sda and scl lines depends on the supply voltage, the bus ca- pacitance, and the number of connected devices with their associated input currents. control of the clock and data lines is done through open drain/collector current-sink outputs, and thus requires external pull-up resistors on both lines. a guideline is bus r p c t r < 2 , where t r is the maximum rise time (minus some margin) and c bus is the total bus capacitance. assuming an i 2 c device on each dimm, an i 2 c controller, the clock buffer, and two other bus devices results in values in the 5k w to 7k w range. use of a series resistor to provide protection against high voltage spikes on the bus will alter the val- ues for r p . figure 21: connections to the serial bus r p sda scl data in data out clock out transmitter data in data out receiver clock in r p r s (optional) r s (optional) r s (optional) r s (optional) 8.3.1 for more information more detailed information on serial bus design can be obtained from smbus and i 2 c bus design , available from the intel corporation at http://www.intel.com. information on the i 2 c-bus can be found in the document the i 2 c-bus and how to use it (including specifica- tions), available from philips semiconductors at http://www-us2.semiconductors.philips.com. additional information on the system management bus can be found in the system management bus specifica- tion, available from the smart battery system implementers forum at http://www.sbs-forum.org.

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